1. Technical Field
The present invention relates to a semiconductor integrated circuit, more particularly, a circuit that corrects the duty cycle of a clock in a semiconductor integrated circuit.
2. Related Art
In general, semiconductor integrated circuits, such as an SDRAM (Synchronous Dynamic Random Access Memory), exhibit improved operational speeds by using a clock in the operation. For this purpose, semiconductor integrated circuits are provided with a clock buffer and use a clock inputted from the outside after buffering it. Although in some cases, semiconductor integrated circuits generate and use an internal clock by themselves, of which the phase difference from an output clock is corrected by a DLL (Delay Locked Loop) circuit or a PLL (Phase Locked Loop) circuit. In a clock used internally in the semiconductor integrated circuits, it is preferable that the ratio of the high period and a low period, that is, the duty ratio is maintained at 50:50. However, a large number of delay elements are provided inside the semiconductor integrated circuits. As a result, the duty ratio of the clock inside is frequently distorted.
As the operational speed of semiconductor integrated circuits increases, the frequency use of a clock gradually increases. As a result, a clock that exhibits a more stable duty ratio is desirable. Accordingly, a semiconductor integrated circuit is provided with a duty cycle correcting circuit therein for stabilizing the duty ratio of a clock and the duty cycle correcting circuit becomes more and more important to stably use a clock in a high-speed operation. The duty cycle correcting circuit falls into an analog type and a digital type. The analog type duty cycle correcting circuit provides an advantage in that it can implement linear control, but suffers a disadvantage in that the region of an operation frequency is limited. On the other hand, the digital type duty cycle correcting circuit can realize an advantage in that the region of an operation frequency is large, but can suffer a disadvantage in that it has difficulty in implementing linear control. As described above, the conventional duty cycle correcting circuits have a technical limit in that they cannot be implemented to enjoy both the advantages realized by analog and digital types. Therefore, it has been continuously required to overcome the technical limit.